Electronic design automation (EDA) tools, a category of computer aided design (CAD) tools, are used by electronic circuit designers to create representations of circuit configurations, including representations of cells (e.g., transistors) and the interconnects they drive. EDA tools allow designers to construct a circuit and simulate its performance using a computer and without requiring the costly and lengthy process of fabrication. EDA tools are indispensable for designing modern, very-large-scale integrated circuits (VSLICs). For this reason, EDA tools are in wide use.
One type of EDA tool, an extraction tool, performs electric circuit extraction, or simply “extraction,” which is a translation of an IC layout back into the electrical circuit (“netlist”) it is intended to represent. Extracted circuits may be needed for various purposes, including circuit simulation and timing analysis, which includes static timing analysis (STA) and statistical timing analysis (SSTA). In extraction, an informal distinction is often made between designed devices, which are devices that are deliberately created by the designer, and parasitic devices, which were not explicitly intended by the designer but are inherent in the layout of the circuit. Accordingly, the typical extraction occurs in three phases: designed device extraction, interconnect extraction, and parasitic device extraction.
Timing signoff is a required step in the design flow that is time consuming, requires iterations of timing analysis to identify critical paths and repairing identified timing violations identified in those critical paths. Unfortunately, this approach has a serious drawback. Since timing analysis (performed with either an STA tool or an SSTA tool) is performed with no reference to the logical behavior of the circuit being analyzed, a significant portion (more than 60%) of the critical paths identified by timing analysis are unsensitizable, i.e., no transition ever propagates along them during normal circuit operation. In other words, more than 60% of the timing violations identified by timing analysis would result in a designer's time being wasted repairing violations that are of no consequence (not “real”). If the designer cannot repair a violation in a critical path, at least that portion of the circuit must be made to operate at a lower speed. If that critical path is unsensitizable, the circuit's performance has been compromised for no good reason. By virtue of having to repair unsensitizable paths, the time, called “tapeout,” at which a circuit is declared ready (“signed off”) for manufacture is delayed, and the performance of the circuit may be impaired.